1. Field of Invention
The disclosure relates to analog-to-digital converter circuits. More particularly, the disclosure relates to an analog-to-digital converter (ADC) that includes an MDAC.
2. Description of Related Art
An analog-to-digital converter (ADC) is a device that takes an analog data signal and converts it into a digital code, i.e. digitizes or quantizes the analog signal. An ADC is a key building block in mixed-mode integrated circuits (ICs). Once the analog signal is converted into the digital domain, complicated signal processing functions can be performed with easier handling and improved noise immunity. In some instances, power dissipation can be reduced since many ADCs are implemented in a deep submicron CMOS process.
ADCs may employ a wide variety of architectures, such as the integrating, successive-approximation, flash, and the delta-sigma architectures. Recently, the pipelined analog-to-digital converter (ADC) has become a popular ADC architecture for use in high-speed applications such as CCD imaging, ultrasound medical imaging, digital video, and communication technologies such as cable modems and fast Ethernet. Pipelined ADCs are typically chosen because of their high accuracy, high throughput rate, and low power consumption. Moreover, the pipelined architecture generally provides better performance for a given power and semiconductor die area than other ADC architectures.
With the digital error correction, the pipelined ADC can tolerate a great comparator offset. However, in the advanced process in which case the supply voltage Vdd becomes lower, it is difficult to achieve a sufficient operating range (i.e. reference voltage), which reduces the tolerable range of the comparator offset.
FIG. 1 and FIG. 2 show part circuit of the conventional pipelined ADC with sample and hold amplifier (SHA) and without SHA. The stage circuit 101 and the sample and hold amplifier (SHA) 113 are generally employed in the conventional pipelined ADC, in which the stage circuit 101 generally includes a analog to digital converter 111 and a MDAC 103 having a simple and hold (S/H) circuit 105, a digital to analog converter 107 and a amplifier 109. In order to provide stabled and synchronized signal for the stage MDAC 103 and sub-ADC 111 in the stage circuit 101 for sampling, the SHA 113 is used. However, the SHA 113 will increase power consumption and noise, therefore, low power pipelined ADC design usually does not adopt SHA 113, and the SHA-less architecture shown in FIG. 2 becomes popular.
However, an unavoidable time difference existing between the S/H 105 and the ADC 107 causes a sampling mismatch, and the signal-dependent offset which increases as fin is thus induced. As a result, the amount of the permissible comparator offset is reduced, and input signal bandwidth of the ADC is thus limited.
FIG. 3 and FIG. 4 show a wave diagram of an output voltage coming from a stage circuit of the pipelined ADC. Point A and the point B of FIG. 3 and FIG. 4 represent the situation in which case the comparator offset exceeds the normal operation range. Because the comparator offset will be amplified by the continuing stages, missing code and serious errors are caused as a result.